Set Reset RS Latch Flip Flop made from two NAND Logic Gates Integrated Circuit IC

Two NAND gate Set/Reset (SR) circuit lets you have one output high while the other output is low. A low (usually close to 0V) signal, applied to either the set or reset, determines which output is high, and which output is low.

NAND gate set reset SR latch flip flop circuit schematic by electronzap
NAND gate set reset SR latch flip flop circuit schematic by electronzap
Brief 7400 74HC00 Quad 2 Input NAND Gate schematic pin layout truth table diagram by electronzap electronzapdotcom
Brief 7400 74HC00 Quad 2 Input NAND Gate schematic pin layout truth table diagram by electronzap electronzapdotcom
  • NAND output will only go low if both inputs are high. If one, or both inputs are low, then the output will be high.
  • One input of both of the NAND gates is held high through a pull up resistor and will stay that way until a low input overpowers it. The other input is set by the other NAND gate’s output.
  • When one NAND gate output is low, then it gives that low signal to the input of the other NAND gate. As long as the other input of the second NAND gate isn’t forced low, then the pull up resistor keeps that input high, and it’s output stays high.
  • Now the second NAND gate feeds it’s high output back to the input of the first NAND gate. Since the first NAND gate’s other input is held high (unless forced low), it has 2 high inputs, which holds its output low.

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