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The 4053 has three multiplexer or demultiplexer circuits with 2 channels. A low signal to a control pin of one of the circuits allows only one of the channels to conduct low power or a signal. Whereas a high signal to the control pin allows the other channel to conduct low power or signal. A high (1) input to the inhibit pin stops all channels from conducting. It is generally held low (0).
Note: The schematic SPDT switches that I drew in the 4053 box represent transistors in the IC, not physical switches.
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